A semiconductor device may include a memory array having a plurality of memory cells. The memory array may act as an electrically programmable read-only memory (EPROM) array, an electrically erasable and electrically programmable read-only memory (EEPROM) array, or a flash electrically erasable and electrically programmable read-only memory (flash EEPROM) array. Memory cells within a memory array that acts as an EPROM array, an EEPROM array, or a flash EEPROM array include electrically programmable read-only memory cells. Memory cells within a memory array that acts as an EEPROM array or a flash EEPROM array are electrically erasable, too. A difference between an EEPROM array and a flash EEPROM array is that the former typically has a memory array with memory cells that are individually erased (one cell at a time) and the latter typically has a memory array with memory cells, wherein a plurality of memory cells are erased simultaneously (during the same erasing sequence).
Many of memory cells within any of these memory arrays each include only one transistor having an active region, a floating gate, and a control gate. As used in this specification, the active region of a memory cell is the combination of the regions that act as the source, channel, and drain regions for the memory cell. Prior art memory cells typically occupy more than one square micron even when the minimum feature size is about 0.5 micron because the source region or the drain region lies adjacent to a side of the channel region.
An active region may include a silicon pillar formed by a trench etch of a silicon substrate. Formation of a memory cell using the trench etch is problematic because endpoint detection cannot be used to signal the end of the etch. Also, any loading effects during the etch may cause the height of the silicon pillars to vary from one device to another and possible between memory cells within the same device.